1. Field of the Invention
The present invention relates to an associative memory, and in particular, it relates to an optimum value detecting circuit which is used to realize a pattern matching function.
2. Description of the Related Art
Conventional optimum value detecting circuits for a semiconductor associative memory are known which have a stabilizing function based on feedback and a fixed maximum gain area. The semiconductor associative memories comprising the optimum value detecting circuit of this kind are proposed by H. J. Mattausch et al., “An Architecture for Compact Associative Memories with Deca-ns Nearest-Match Capability up to Large Distances”, ISSCC Dig. Of Tech. Papers, pp. 170-171, 2001, and by Jpn. Pat. Appln. No. 2002-008783, for example.
An operation of the conventional optimum value detecting circuit, especially a winner lineup amplifier (hereinafter simply referred to as WLA) which amplifies a winner-loser distance will be described using FIG. 8. It should be noted that the semiconductor associative memory optimally retrieves the most analogous reference data to input data from reference data stored in a memory area on the basis of a scale called a distance between data. The optimum here means, for example, that the distance is the maximum or minimum. The reference data retrieved in accordance with the input data is called a winner, and the reference data that is not retrieved is called a loser. In addition, the WLA represents a winner-loser distance amplifying section directly concerned with data retrieval capability and its peripheral circuit sections, in the optimum value detecting circuit except for the memory area of the associative memory.
FIG. 8 is a diagram showing a block configuration of the conventional WLA. The WLA shown in FIG. 8 is constituted by signal control sections (SR) 100 which input a comparison signal Ci (indicated as i=1, . . . , R in FIG. 8) from a word weighted comparator WWCi (not shown) belonging to a cell array in an i row of the associative memory, and a circuit block (AFG) 200 comprising the winner-loser distance amplifying section having a fixed maximum gain area and a feedback generating section.
The signal control section (SR) 100 converts a current intensity of the comparison signal Ci into a signal voltage. At the same time, it comprises a function of adjusting this signal voltage to an intermediate potential VIi of the fixed maximum gain area of the winner-loser distance amplifying section. In this way, a signal LAi used to finally obtain a digital retrieval result is output from the circuit block (AFG) 200.
On the other hand, feedback signals F to the signal control section (SR) 100 and the word weighted comparator WWCi are generated by the feedback generating section incorporated in the circuit block (AFG) 200, thereby securing a stable operation of the WLA.
However, disadvantages of the conventional WLA lie in the fact that since a minimum distance input signal (comparison signal Ci) is amplified in the fixed maximum gain area and its operation is stabilized by the feedback, there is a limit in the range of stabilization control, and power consumption is increased. Moreover, in a conventionally applied feedback circuit, a load capacity of the signal control section increases if a number R of input signals Ci is increased, which has prevented high-speed operation.
As described above, the problem of the conventional WLA is that the fixed maximum gain area limits the stabilization control range, and that the power consumption is increased.
The present invention has been attained to solve the above-mentioned problems, and an object thereof is to provide a WLA which has a larger control range in the feedback stabilization, comprises a self-adjusting function of the maximum gain area, and linearly increases the number of transistors in response to an increase in the number of reference data (number of rows in the memory).